Ermont, Jérôme, Mouysset, Sandrine, Scharbarg, Jean-Luc and Fraboul, Christian (2018) Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture. In: 26th International Conference on Real-Time Networks and Systems (RTNS’2018), 10-12/10/2018, Poitier.

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Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500 $\mu s$. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisioned for future avionics architecture. The principle is to distribute avionics functions on these many-cores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500 us. A first solution has been proposed, where each function manages the transmission of its VLs. The idea of this solution is to distribute functions on each many-core in order to minimize contentions for VLs which concern functions allocated on different many-cores. In this paper, we consider that VL transmissions are managed by a single task in each many-core. We propose to construct a scheduling table executed by this task using an Integer Linear Program. The access to the Ethernet interface is then only allowed to one VL leading to a significant reduction of the jitter.

Item Type: Conference or Workshop Item (Paper)
Language: English
Date: 2018
Additional Information: Thanks to the Association for Computing Machinery (ACM). This paper appears in RTNS '18 Proceedings of the 26th International Conference on Real-Time Networks and Systems. ISBN: 978-0-7918-5461-7. The original PDF is available at:
Uncontrolled Keywords: Network-on-Chip - AFDX - ILP - Bin Packing Problem - Jitter
Divisions: Institut de Recherche en Informatique de Toulouse
Site: UT1
Date Deposited: 16 Jan 2019 08:17
Last Modified: 02 Apr 2021 15:58
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